1. Field of the Invention
The present invention relates to MOS transistors and, more particularly, to a radiation hardened MOS transistor.
2. Description of the Related Art
FIG. 1A shows a plan view that illustrates a prior-art NMOS transistor 100, and a prior-art NMOS transistor 102 that is formed adjacent to transistor 100. FIG. 1B shows a cross-sectional diagram taken along line 1B-1B of FIG. 1A.
As shown in FIGS. 1A and 1B, transistors 100 and 102, which are formed in a p-type substrate 110, both have spaced-apart n+ source and drain regions 112 and 114 that are formed in substrate 110. Both transistors 100 and 102 also have a channel region 116 that is located between the source and drain regions 112 and 114. The source and drain regions 112 and 114, and channel region 116 of each transistor define an active region for each transistor.
In addition, a field oxide region FOX is formed in substrate 110. Field oxide region FOX surrounds the active regions, isolating the active region of transistor 100 from the active region of transistor 102. Transistors 100 and 102 both further have a gate oxide layer 120 that is formed over channel region 116, and a gate 122 that is formed on gate oxide layer 120 over channel region 116, and on a portion of field oxide region FOX.
A local interconnect 124 can also be formed on the top surface of field oxide region FOX. This structure can form a parasitic MOS transistor where drain region 114 of transistor 100 functions as the drain, source region 112 of transistor 102 functions as the source, field oxide region FOX functions as the gate oxide layer, and interconnect 124 functions as the gate. To prevent the formation of a parasitic transistor, field oxide region FOX is formed to have a thickness that prevents the substrate region lying below field oxide region FOX from inverting when a positive voltage is applied to interconnect 124.
When ionizing radiation from outer space passes through the semiconductor materials that form transistor 100, such as silicon and oxide, the radiation causes electron-hole pairs to be formed in the semiconductor material. The electron-hole pairs formed in silicon typically recombine quickly and, as a result, pose little problem to the operation of transistor 100.
However, when the electron-hole pairs are formed in field oxide region FOX, the holes often become trapped within the oxide. The traps are widely believed to be caused by lattice defects that occur during the formation of the field oxide region FOX by the local oxidation of silicon (LOCOS) process.
With the LOCOS process, a layer of pad or buffer oxide is formed over the substrate, followed by the formation of an overlying layer of nitride. Selected portions of the layer of nitride and the underlying layer of pad oxide are then removed to expose portions of the silicon substrate where the field oxide regions are to be formed. After this, a channel-stop implant is performed, followed by the thermal growth of the field oxide regions.
As the oxide grows, however, the oxide pushes against the sides of the nitride/oxide openings. The stiffness of the nitride layer restrains the oxide from growing upward, thereby causing downward stress against the silicon along the corner of the growing oxide. Further stress along the corner is caused by the volume misfit of the growing oxide. These stresses, in turn, generate dislocations in the silicon.
Although it is difficult to characterize the exact nature of the stress-induced damage discussed above, the lattice defects are thought to trap holes. The accumulation of holes at the trap sites produces positive charges at the trap sites. The positive charges attract electrons in substrate 110 to the surface of field oxide region FOX, and can invert the region adjacent to field oxide region FOX.
When the positive charge trap sites lie at the edge of field oxide region FOX adjacent to the active region under gate 122, electrons are attracted to the surface of field oxide region FOX under gate 122. The electrons invert the surface and form a drain-to-source field edge leakage current 126 that allows electrons to flow from source region 112 to drain region 114 when no gate bias is applied. The drain-to-source field edge leakage current consumes power and can be large enough to lead to device failure.
When the positive charge trap sites lie in field oxide region FOX below interconnect 124 between drain region 114 of transistor 100 and source region 112 of transistor 102, electrons 130 are attracted to the bottom surface of field oxide region FOX. The accumulation of electrons along the bottom surface of field oxide region FOX effectively lowers the threshold voltage of the parasitic MOS transistor.
As a result, the parasitic MOS transistor can turn on, allowing a device-to-device field leakage current 128 to flow from region 114 of transistor 100 to region 112 of transistor 102, when a positive voltage is applied to interconnect 124. Thus, there is a need to increase the radiation hardness of MOS transistors.
The present invention provides a transistor that substantially increases the radiation hardness of MOS transistors by eliminating the drain-to-source field edge leakage current. The present invention also reduces the device-to-device field leakage current, which results from the lowering of the threshold voltage of a parasitic MOS transistor that utilizes the field oxide region as the gate oxide.
A transistor in accordance with the present invention is formed in a semiconductor material of a first conductivity type, and has an upper surface. The transistor includes a first region of a second conductivity type that is formed in the semiconductor material, and a second region of the second conductivity type that is formed in the semiconductor material a distance apart from the first region.
The transistor also includes a first channel region of the semiconductor material that is located between the first region and the second region. The transistor further includes a third region of the second conductivity type that is formed in the semiconductor material a distance apart from the first region and the second region.
In addition, the transistor includes a second channel region of the semiconductor material that is located between the second region and the third region. An active region is defined by the first region, the second region, the third region, the first channel region, and the second channel region.
The transistor additionally include a fourth region of the second conductivity type that is formed in the semiconductor material a distance apart from the active region. The fourth region has an upper surface that surrounds the upper surface of the active region. The transistor further includes a third channel region of the semiconductor material that is located between the fourth region and the active region.
In addition, the transistor includes a gap region of the semiconductor material that has an upper surface that adjoins the upper surface of the fourth region. The transistor further includes a field oxide region that is formed in the semiconductor material. The field oxide region surrounds the upper surface of the fourth region, and adjoins the gap region.
In addition, a gate is formed over the first channel region, the second channel region, and the third channel region. The transistor can further include a second gate that is formed over a portion of the gap region. Alternately, the upper surface of the gap region can adjoin and surround all of the fourth region, and the gate can also be formed over all of the gap region. Further, the upper surface of the gap region can adjoin and surround all of the fourth region, a first gate can be formed over the first, second, and third channel regions, and a second gate can be formed over a portion of the gap region.